Heteroepitaxy refers to growth of single crystal thin layers on substrates of different lattice constants (or atomic spacing). If achievable, high quality semiconductor heteroepitaxial layers have many important applications in electronics and optoelectronics. Their benefits include enhanced speed and power efficiency for RF amplifiers in wireless communication, and enhanced quantum efficiency and operating wavelength range for optoelectronic devices such as lasers, LEDs, and detectors. However, in reality, with exceptions of very few cases, the great potential benefits of heteroepitaxial films can not be realized because the heteroepitaxial layers achievable today contain a large number of defects, specifically threading dislocations. These dislocations in the heteroepitaxial layers degrade device performance and reliability so much that heteroepitaxy is rarely used for any commercial applications. Therefore, to realize the great potential of heteroepitaxy, it is imperative to find ways to significantly reduce the number of threading dislocations in the heteroepitaxial layers.
U.S. Pat. No. 5,294,808 (Lo) requires ultra thin substrates or a sacrificial substrate for dislocation gettering. U.S. Pat. No. 5,091,133 (Fan et al.) uses thermal stress from thermal annealing/cycling by interrupting the growth. The stress produced in the method of the '133 patent only exists during thermal annealing. U.S. Pat. No. 5,659,187 (Legoues et al.) discloses a method wherein the dislocation bending force is only over the strain graded buffer layers. Furthermore, new dislocations may be nucleated in the strain graded buffer layers as they bend the existing dislocations.
Referring to FIG. 1, when a heteroepitaxial thin film 5 is grown on a substrate 8, its lattice is initially deformed elastically to match that of the substrate. Hence the stress in the heteroepitaxial material builds up as the film 5 grows thicker. At a certain film thickness, namely the critical thickness, the strain energy is too high to be accommodated by elastic deformation and the thin film becomes plastically deformed by forming dislocations. According to the well established theory, dislocations are most likely nucleated at the surface 7 of the heteroepitaxial layer and then propagate towards the film-substrate interface 6 to become misfit dislocations for strain release. The strain releasing misfit dislocations may be extended over a finite distance until they either reach the edge of the wafer or most likely thread up to the surface 7 of the heteroepitaxial layer.
The formation of the above described "dislocation half loop", shown at 30, consists of a section of misfit dislocation 10 and two threading dislocations 20, 21. The misfit dislocation 10 portion of the dislocation half loop 30 relaxes the strain and does no harm to devices built in the heteroepitaxial layers since it is confined at the interface. However, the threading dislocation portions 20, 21 of the half loop 30 run across the entire thickness of the film, thus being detrimental to devices. Therefore, the key to improving the quality of heteroepitaxial film is to minimize the density of threading dislocations while keeping the misfit dislocations for strain release.